The present invention relates to a semiconductor device including bump electrodes, a manufacturing method and a testing method of the same, and also relates to a liquid crystal display device, a circuit substrate and a tape carrier package (hereinafter referred to as TCP), respectively, including the semiconductor device.
Known methods of electrically connecting a semiconductor device to a liquid crystal display device, a circuit substrate or a TCP include a wireless bonding method wherein a bump electrode is provided on an electrode terminal of a semiconductor device, and the semiconductor device is bonded directly to the liquid crystal display device, the circuit substrate or the TCP using the bump electrode.
A concrete example will be given through the case of the liquid crystal display device of a chip-on-glass (hereinafter referred to as COG) method wherein a liquid crystal driver chip as a semiconductor device is directly face-down-bonded to a liquid crystal panel. The described COG method is classified into two types: (i) a paste COG method wherein the liquid crystal driver chip and the liquid crystal panel are connected by means of an electrically conductive paste; and (ii) an ACF-COG method wherein the liquid crystal driver chip and the liquid crystal panel are connected by means of an anisotropic electrically conductive film (hereinafter referred to as ACF).
As shown in FIG. 13(a), a liquid crystal driver chip Axe2x80x2 includes a semiconductor base 101 whereon an insulating film 102, an electrode pad 103, and a protective film 104 with an opening are laminated in this order. On the opening, a bump electrode 106 is formed via a barrier metal 105. On the other hand, a liquid crystal panel Bxe2x80x2 on which the described liquid crystal drive chip Axe2x80x2 is to be bonded includes a glass substrate 109 whereon a conductive pattern 110 and a protective film 111 are laminated in this order.
In the paste COG method, after a conductive paste 112 is applied to the bump electrode 106 of the liquid crystal driver chip Axe2x80x2, the liquid crystal driver chip Axe2x80x2 is face-down-bonded to the liquid crystal panel Bxe2x80x2. Then, the conductive paste 112 is cured, thereby connecting the bump electrode 106 and input and output terminals of the conductive pattern 110.
On the other hand, in the ACF-COG method, as shown in FIG. 13(b), an ACF composed of a binder resin 107 and conductive particles 108 is enclosed in a spacing formed between the liquid crystal driver chip Axe2x80x2 and the liquid crystal panel Bxe2x80x2, thereby connecting the bump electrode 106 and the input and output terminals of the conductive pattern 110 via the conductive particles 108.
However, the described COG method wherein the liquid crystal driver chip is directly face-down-bonded to the liquid crystal panel has a drawback in that a mounting inferior occurs when mounting the panel due to a bump inferior such as a bump defect, irregularity in bump height, etc.
Moreover, in the COG method, as the bump electrode is bonded to a hard material such as glass, etc., irregularity in height of bumps within the liquid crystal driver chip would cause a problem. For example, in the case of the ACF-COG method, the conductive particles in the ACF has an average particle diameter in a range of from 3 to 5 xcexcm, and thus if a gap between heights of the adjoining bump electrodes is larger than the diameter of the conductive particle, an inferior connection occurs. Also, in the case of the paste COG method, if a gap between heights of the adjoining bump electrodes is larger than the thickness of the paste to be applied, an inferior connection occurs.
When adopting the COG method, in order to prevent an increase in a contact resistance, or contact due to an unexpected bump defect, a multiple port structure is generally adopted for the power source terminal and the input terminal. For the output terminal, however, in consideration of a space required, etc., the multiple port structure is not adopted.
Therefore, even when only one of the bump electrodes on the output terminal is defective, or significantly lower than the adjoining bump electrode (by not less than a conductive particle diameter), a panel display defect such as a line defect, etc., occurs, or fixing of the defective bump electrode is required or is discarded.
The described problem occurs not only in the liquid crystal display device of the COG method but also in the circuit substrate wherein the semiconductor chip is face-down-bonded to the substrate main body such as a print substrate, a ceramic substrate, etc. Such problem occurs because the substrate main body to which the bump electrode is bonded is made of a hard material.
The TCP has advantageous features over other face-down-bonding method in that (i) the inner lead is flexible, and (ii) an eutectic crystal is generated by the bump electrode and (Tin) plated onto the inner lead, and the inner lead is inserted into the bump electrode. However, even for the described TCP, for example, if a bump defect occurs, or a significant gap in bump height is generated, an inferior connection cannot be avoided.
In order to counteract the described problem, as shown in FIG. 14, Japanese Unexamined Utility Model Publication No. 56136/1991 (Jitsukaihei 3-56136) discloses a bonding bump wherein four divided gold bumps (bump electrodes) 206a, 206b, 206c and 206d are formed on a square connection terminal (electrode pad) 206. According to the described arrangement, a semiconductor chip is bonded to a substrate terminal by means of a curing resin around the metal bump. Therefore, by dividing the metal bump into four, an occurrence of an inferior connection due to residual resin remaining between (a) the metal bumps 206a, 206b, 206c and 206d, and (b) the substrate terminal can be avoided.
However, the described arrangement of Japanese Unexamined Utility Model Publication No. 56136/1991 has a drawback in that as the bump electrode is divided bidirectionally along a column and a row, narrowing of an electrode pad pitch, i.e., a wiring pitch, is not possible.
Moreover, the arrangement wherein the bump electrode composed of a transferred bump substrate is directly bonded to the semiconductor chip like the case of the above Gazette cannot be applied when the electrode pad pitch is not more than 100 xcexcm. Recently, as an electrode pad pitch of 50 to 80 xcexcm has been generally adopted to meet a demand for a miniaturization of a semiconductor chip, the described method cannot be used in practical applications.
The described mechanism is the same as the following mechanism. The generally used transfer bump adopts an inner lead bonding method wherein the bump electrode is transferred to a leading end of the inner lead of the tape carrier, and the bump electrode thus transferred is inner-lead-bonded to the electrode pad of the semiconductor chip. Although this method has an advantageous feature that a wafer bump process can be omitted, a mechanical connection is repeated twice, thus it is not practical to use the method for the electrode pad pitch of not more than 100 xcexcm in view of precision. Therefore, in consideration of the fact that a mechanical connection is required, and the described transferring of the bump electrode can be performed only chip by chip, a wafer bump method wherein the bump electrode is formed on the electrode pad of the semiconductor chip in the wafer bump process is superior to the transfer bump method in view of both precision and mass production.
As to the divided bump electrodes, Japanese Unexamined Patent Publication No. 13418/1993 (Tokukaihei 5-13418) and Japanese Unexamined Patent Publication No. 58112/1995 (Tokukaihei 7-58112) disclose four divided bump electrodes for the purpose of suppressing a generation of a thermal stress.
However, neither of described Gazettes teach two divided bump electrodes or a mounting structure which offers a lower rate of inferior results such as a bump defect, etc. These Gazettes also fail to refer to the wiring pitch. Especially, Japanese Unexamined Patent Publication No. 13418/1993 (Tokukaihei 5-13418) discloses the arrangement wherein a solder layer is formed on the bump electrode. According to the described arrangement, even when only one of the bump electrodes is defective, the solder layer cannot be formed in a shape as desired, and an occurrence of an inferior bump cannot be suppressed. On the other hand, Japanese Unexamined Patent Publication No. 58112/1995 (Tokukaihei 7-58112) discloses the diode element only, and does not refer to the concept of the wiring pitch.
It is an object of the present invention to provide a semiconductor device which suppresses an occurrence of a defect such as a bump defect, etc., and enables a narrowing of an electrode pad pitch.
In order to achieve the above object, the semiconductor device of the preset invention includes a semiconductor substrate; a plurality of electrode pads aligned in parallel on the semiconductor substrate; and a plurality of bump electrodes placed on each of the plurality of electrode pads, the plurality of bump electrodes placed on the electrode pad being aligned in a direction orthogonal to the direction where the electrode pads are aligned.
According to the described arrangement, as a plurality of divided bump electrodes are provided for each electrode pad, compared with the case of adopting a single bump electrode, an occurrence of a defective bump electrode can be suppressed. Namely, in the case of a single bump electrode, if a bump defect occurs, or a significant gap is generated between heights of the adjoining bump electrodes, etc., an inferior connection occurs when mounting the semiconductor device. However, in the case of adopting a plurality of divided bump electrodes, even if a bump defect or a gap between heights of the adjoining bump electrodes occurs in some of the plurality of divided bump electrodes, as long as at least one bump electrode is connected, an occurrence of the inferior connection can be avoided. As the described arrangement permits a significantly lower proportion of inferior connections when mounting the semiconductor device, an improved yield in manufacturing the bump electrodes and an improved reliability of connections can be achieved.
Furthermore, as the plurality of bump electrodes are aligned in a direction orthogonal to the direction where the electrode pads are aligned, an interval between the electrode pads can be reduced to the minimum. This permits a narrower electrode pad pitch, which in turn results in the size of a semiconductor device being reduced.
It is another object of the present invention to provide a manufacturing method of a semiconductor device of the present invention which permits bump electrodes to be prepared at a significantly improved yield.
In order to achieve the above object, the manufacturing method of the semiconductor device of the present invention is characterized by including the steps of: patterning a photoresist which serves as a bump electrode forming use mask on the semiconductor substrate having formed thereon the electrode pads, to be thicker than the bump electrodes; and
plating the bump electrode forming use metal on an electrode pad to form a bump electrode in a perpendicular straight wall shape, to be thinner than the photoresist.
According the described method, mutual effects among the plurality of bump electrodes when plating can be eliminated, thereby achieving a significantly improved yield of the bump electrodes.
It is still another object of the present invention to provide a testing method of a semiconductor device of the present invention which permits an occurrence of an abnormality in shape of a bump electrode to be suppressed to the minimum.
In order to achieve the above object, the testing method of the semiconductor device of the present invention is characterized by including the step of performing an electrical characteristic test by making a test prober in contact with a bump electrode formed on the inner most side of the semiconductor substrate of the plurality of bump electrodes.
When carrying out the electrical characteristic test, in order to ensure a contact between the bump electrodes and the test prober, a pressure is applied after the test prober is made in contact with the bump electrode. Therefore, the test prober tends to move inside of the chip. Here, in the arrangement where the test prober is made in contact with the outer bump electrode, if of the bump electrode is missed, the prober would push the base portion of the inner bump, which may cause a missing of the inner bump as well. Furthermore, when the test prober is made in contact with the outer bump electrode, in an event of a deformation of the bump electrode due to some trouble, the deformation of the outer bump electrode may cause the inner electrode to be deformed.
In order to counteract the described problems, the method of testing the semiconductor device in accordance with the present invention is arranged such that the test prober is made in contact with the bump electrode formed on the inner most side. As a result, even in an event of an abnormality in an applied pressure to a probe needle, the defective bump in its shape due to a mechanical strength applied when testing using the test prober can be suppressed to the minimum.
The novel features which are considered as characteristic of the invention are set forth in particular in the appended claims. The improved treatment method, as well as the construction and mode of operation of the improved treatment apparatus, will, however, be best understood upon perusal of the following detailed description of certain specific embodiments when read in conjunction with the accompanying drawings.